Ansys Q3D Workflow — Lesson 2

In every simulation process, defining the workflow is necessary to make a simulation design efficient. The workflow in Q3D is like other Ansys products contained in Ansys Electronics Desktop (AEDT). In this lesson, you will learn the basics of a simulation setup workflow.

This lesson consists of one lecture and three workshops.

The lecture covers the Q3D extractor workflow process. It introduces the materials or boundaries, nets, terminals, solution setup and results. The Q3D workflow can be broadly categorized into two parts:

Part 1: Setting up and running the simulation

Part 2: Analyzing the simulation result


Workshop 2.1

This workshop covers the simulation aspects of parallel plate capacitance over a ground. The outline of this workshop is as follows:
Invoke AEDT >> open parallel plate capacitance design >> specify boundary conditions >> set up nets >>define sources and sinks >> create a solution setup >> validate and simulate design >> view capacitance matrix.



Workshop 2.2

This workshop covers the simulation aspects of busbar inductance. The outline of this workshop is as follows:
Invoke AEDT and open Q3D example >> set up nets >>define sources and sinks >> create a solution setup >> simulate the design >> plot data table of AC and DC inductance >> add frequency sweep >> resimulate the design >> plot AC and DC inductance over frequency.


Workshop 2.3

This workshop covers the simulation aspects of a Z-bend. The outline of this workshop is as follows:
Invoke AEDT and open Q3D example >> setup nets >> assign sources and sinks >> create an analysis solution setup >> validate and simulate >> view capacitance matrices >> perform ground net matrix reduction operation >> export equivalent circuit.

Simulation Files

Download the accompanying simulation files here.